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			<SFW>01.96</SFW>
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			<MON>03.04</MON>
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			<MON>03.04</MON>
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			<MON>03.04</MON>
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			<SFW>01.90</SFW>
			<ILO>01.52.01</ILO>
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			<MON>03.04</MON>
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			<SFW>01.90</SFW>
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			<MON>03.04</MON>
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			<Name>26.30</Name>
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			<MON>03.04</MON>
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			<Name>26.13</Name>
			<SFW>01.80</SFW>
			<ILO>01.43.01</ILO>
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			<MON>03.04</MON>
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			<Name>26.12</Name>
			<SFW>01.80</SFW>
			<ILO>01.41.01</ILO>
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			<MON>03.04</MON>
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			<MON>03.04</MON>
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			<Name>26.05</Name>
			<SFW>01.72</SFW>
			<ILO>01.40.42</ILO>
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			<MON>03.04</MON>
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			<SFW>01.60</SFW>
			<ILO>01.40.32</ILO>
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			<MON>03.04</MON>
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			<Name>25.01</Name>
			<SFW>01.60</SFW>
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			<MON>03.04</MON>
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			<SFW>01.40</SFW>
			<ILO>01.40.23</ILO>
			<FPGA>02.00</FPGA>
			<MON>03.04</MON>
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			<Name>23.00</Name>
			<SFW>01.30</SFW>
			<ILO>01.40.11</ILO>
			<FPGA>02.00</FPGA>
			<MON>03.04</MON>
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			<SFW>01.25</SFW>
			<ILO>01.40.02</ILO>
			<FPGA>01.14</FPGA>
			<MON>03.04</MON>
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			<Name>21.08</Name>
			<SFW>01.24</SFW>
			<ILO>01.30.30</ILO>
			<FPGA>01.14</FPGA>
			<MON>03.04</MON>
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			<Name>21.06</Name>
			<SFW>01.24</SFW>
			<ILO>01.30.30</ILO>
			<FPGA>01.14</FPGA>
			<MON>03.04</MON>
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			<Name>21.04</Name>
			<SFW>01.24</SFW>
			<ILO>01.30.29</ILO>
			<FPGA>01.14</FPGA>
			<MON>03.04</MON>
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			<Name>21.03</Name>
			<SFW>01.24</SFW>
			<ILO>01.30.29</ILO>
			<FPGA>01.14</FPGA>
			<MON>03.04</MON>
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			<Name>21.02</Name>
			<SFW>01.24</SFW>
			<ILO>01.30.28</ILO>
			<FPGA>01.14</FPGA>
			<MON>03.04</MON>
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			<Name>21.01</Name>
			<SFW>01.23</SFW>
			<ILO>01.30.27</ILO>
			<FPGA>01.14</FPGA>
			<MON>03.04</MON>
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			<Name>20.00</Name>
			<SFW>01.20</SFW>
			<ILO>01.30.12</ILO>
			<FPGA>01.14</FPGA>
			<MON>03.04</MON>
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			<Name>19.03</Name>
			<SFW>01.19</SFW>
			<ILO>01.30.01</ILO>
			<FPGA>01.12</FPGA>
			<MON>03.04</MON>
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			<Name>17.01</Name>
			<SFW>01.14</SFW>
			<ILO>01.20.08</ILO>
			<FPGA>01.12</FPGA>
			<MON>03.04</MON>
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			<Name>17.00</Name>
			<SFW>01.12</SFW>
			<ILO>01.20.06</ILO>
			<FPGA>01.12</FPGA>
			<MON>03.04</MON>
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			<Name>16.00</Name>
			<SFW>01.10</SFW>
			<ILO>01.20.02</ILO>
			<FPGA>01.12</FPGA>
			<MON>03.04</MON>
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			<Name>15.05</Name>
			<SFW>01.08</SFW>
			<ILO>01.01.02</ILO>
			<FPGA>01.12</FPGA>
			<MON>03.04</MON>
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			<Name>15.04</Name>
			<SFW>01.07</SFW>
			<ILO>01.01.02</ILO>
			<FPGA>01.12</FPGA>
			<MON>03.04</MON>
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			<Name>15.03</Name>
			<SFW>01.07</SFW>
			<ILO>01.01.02</ILO>
			<FPGA>01.12</FPGA>
			<MON>03.04</MON>
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			<Name>14.2</Name>
			<SFW>01.02</SFW>
			<ILO>01.00.04</ILO>
			<FPGA>01.10</FPGA>
			<MON>03.04</MON>
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			<Name>14.0</Name>
			<SFW>00.94</SFW>
			<ILO>52.25.04</ILO>
			<FPGA>01.10</FPGA>
			<MON>03.04</MON>
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			<Name>13.2</Name>
			<SFW>00.93</SFW>
			<ILO>52.24.06</ILO>
			<FPGA>01.10</FPGA>
			<MON>03.04</MON>
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			<Name>13.1</Name>
			<SFW>00.90</SFW>
			<ILO>52.23.02</ILO>
			<FPGA>01.08</FPGA>
			<MON>03.04</MON>
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			<Name>12.1</Name>
			<SFW>00.87</SFW>
			<ILO>52.22.07</ILO>
			<FPGA>01.07</FPGA>
			<MON>03.04</MON>
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			<Name>12.0</Name>
			<SFW>00.87</SFW>
			<ILO>52.22.06</ILO>
			<FPGA>01.07</FPGA>
			<MON>03.04</MON>
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			<Name>11.2</Name>
			<SFW>00.84</SFW>
			<ILO>52.21.01</ILO>
			<FPGA>01.06</FPGA>
			<MON>03.04</MON>
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			<Name>11.1</Name>
			<SFW>00.82</SFW>
			<ILO>52.21.01</ILO>
			<FPGA>01.06</FPGA>
			<MON>03.04</MON>
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			<Name>10.1</Name>
			<SFW>00.78</SFW>
			<ILO>52.20.03</ILO>
			<FPGA>01.03</FPGA>
			<MON>03.03</MON>
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			<Name>9.0</Name>
			<SFW>00.76</SFW>
			<ILO>52.19.05</ILO>
			<FPGA>01.02</FPGA>
			<MON>03.03</MON>
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			<Name>8.1</Name>
			<SFW>00.72</SFW>
			<ILO>52.18.05</ILO>
			<FPGA>01.01</FPGA>
			<MON>03.03</MON>
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			<Name>8.0</Name>
			<SFW>00.70</SFW>
			<ILO>52.18.03</ILO>
			<FPGA>01.00</FPGA>
			<MON>03.03</MON>
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			<Name>7.3</Name>
			<SFW>00.65</SFW>
			<ILO>52.17.09</ILO>
			<FPGA>00.14</FPGA>
			<MON>03.03</MON>
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			<Name>7.1d</Name>
			<SFW>00.62</SFW>
			<ILO>52.17.11</ILO>
			<FPGA>00.14</FPGA>
			<MON>03.03</MON>
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			<Name>7.1c</Name>
			<SFW>00.62</SFW>
			<ILO>52.17.09</ILO>
			<FPGA>00.14</FPGA>
			<MON>03.03</MON>
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			<Name>7.1</Name>
			<SFW>00.62</SFW>
			<ILO>52.17.03</ILO>
			<FPGA>00.14</FPGA>
			<MON>03.03</MON>
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			<Name>6.1</Name>
			<SFW>00.58</SFW>
			<ILO>52.16.09</ILO>
			<FPGA>00.14</FPGA>
			<MON>03.03</MON>
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			<Name>5.3</Name>
			<SFW>00.56</SFW>
			<ILO>52.15.03</ILO>
			<FPGA>00.13</FPGA>
			<MON>01.03</MON>
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			<Name>5.1</Name>
			<SFW>00.54</SFW>
			<ILO>52.15.03</ILO>
			<FPGA>00.13</FPGA>
			<MON>01.03</MON>
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			<Name>4.0</Name>
			<SFW>00.51</SFW>
			<ILO>52.14.03</ILO>
			<FPGA>00.11</FPGA>
			<MON>01.03</MON>
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			<Name>3.3</Name>
			<SFW>00.48</SFW>
			<ILO>52.13.03</ILO>
			<FPGA>00.11</FPGA>
			<MON>01.03</MON>
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			<Name>3.1</Name>
			<SFW>00.47</SFW>
			<ILO>52.13.02</ILO>
			<FPGA>00.11</FPGA>
			<MON>01.03</MON>
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			<Name>3.0</Name>
			<SFW>00.47</SFW>
			<ILO>52.13.02</ILO>
			<FPGA>00.11</FPGA>
			<MON>01.03</MON>
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			<Name>2.0</Name>
			<SFW>00.45</SFW>
			<ILO>52.12</ILO>
			<FPGA>0.a</FPGA>
			<MON>01.03</MON>
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			<Name>1.0</Name>
			<SFW>00.43</SFW>
			<ILO>52.09</ILO>
			<FPGA>0.7</FPGA>
			<MON>01.03</MON>
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