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  <file_revision>1.31</file_revision>
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      <Name>44.01</Name>
      <SFW>02.61</SFW>
      <ILO>01.62.05</ILO>
      <FPGA>2.02</FPGA>
      <MON>02.09</MON>
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      <Name>43.01</Name>
      <SFW>02.40</SFW>
      <ILO>01.61.04</ILO>
      <FPGA>2.02</FPGA>
      <MON>02.09</MON>
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      <Name>42.05</Name>
      <SFW>02.29</SFW>
      <ILO>01.60.07</ILO>
      <FPGA>2.02</FPGA>
      <MON>02.09</MON>
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    <recipe>
      <Name>42.03</Name>
      <SFW>02.28</SFW>
      <ILO>01.60.07</ILO>
      <FPGA>2.02</FPGA>
      <MON>02.09</MON>
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      <Name>42.02</Name>
      <SFW>02.27</SFW>
      <ILO>01.60.07</ILO>
      <FPGA>2.02</FPGA>
      <MON>02.09</MON>
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    <recipe>
      <Name>42.02</Name>
      <SFW>02.27</SFW>
      <ILO>01.60.06</ILO>
      <FPGA>2.02</FPGA>
      <MON>02.09</MON>
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    <recipe>
      <Name>42.01</Name>
      <SFW>02.26</SFW>
      <ILO>01.60.04</ILO>
      <FPGA>2.02</FPGA>
      <MON>02.09</MON>
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    <recipe>
      <Name>42.00</Name>
      <SFW>02.25</SFW>
      <ILO>01.60.04</ILO>
      <FPGA>2.02</FPGA>
      <MON>02.09</MON>
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      <Name>41.00</Name>
      <SFW>02.24</SFW>
      <ILO>53.80.05</ILO>
      <FPGA>2.02</FPGA>
      <MON>02.09</MON>
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      <Name>40.00</Name>
      <SFW>02.23</SFW>
      <ILO>53.70.02</ILO>
      <FPGA>2.02</FPGA>
      <MON>02.09</MON>
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      <Name>39.00</Name>
      <SFW>02.21</SFW>
      <ILO>53.60.03</ILO>
      <FPGA>2.01</FPGA>
      <MON>02.09</MON>
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      <Name>38.01</Name>
      <SFW>02.19</SFW>
      <ILO>53.50.02</ILO>
      <FPGA>2.01</FPGA>
      <MON>02.09</MON>
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    <recipe>
      <Name>38.00</Name>
      <SFW>02.17</SFW>
      <ILO>53.50.02</ILO>
      <FPGA>2.01</FPGA>
      <MON>02.09</MON>
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      <Name>37.00</Name>
      <SFW>02.16</SFW>
      <ILO>53.40.03</ILO>
      <FPGA>2.01</FPGA>
      <MON>02.09</MON>
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      <Name>36.00</Name>
      <SFW>02.15</SFW>
      <ILO>53.30.02</ILO>
      <FPGA>2.01</FPGA>
      <MON>02.09</MON>
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      <Name>35.00</Name>
      <SFW>02.14</SFW>
      <ILO>53.20.02</ILO>
      <FPGA>2.01</FPGA>
      <MON>02.09</MON>
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      <Name>34.00</Name>
      <SFW>02.13</SFW>
      <ILO>53.10.02</ILO>
      <FPGA>2.00</FPGA>
      <MON>02.09</MON>
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      <Name>33.00</Name>
      <SFW>02.12</SFW>
      <ILO>53.00.91</ILO>
      <FPGA>2.00</FPGA>
      <MON>02.09</MON>
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      <Name>32.01</Name>
      <SFW>02.11</SFW>
      <ILO>53.00.82</ILO>
      <FPGA>2.00</FPGA>
      <MON>02.09</MON>
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    <recipe>
      <Name>32.00</Name>
      <SFW>02.10</SFW>
      <ILO>53.00.82</ILO>
      <FPGA>2.00</FPGA>
      <MON>02.09</MON>
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      <Name>31.00</Name>
      <SFW>02.07</SFW>
      <ILO>53.00.71</ILO>
      <FPGA>2.00</FPGA>
      <MON>02.09</MON>
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      <Name>30.00</Name>
      <SFW>02.06</SFW>
      <ILO>53.00.62</ILO>
      <FPGA>2.00</FPGA>
      <MON>02.09</MON>
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      <Name>29.01</Name>
      <SFW>02.05</SFW>
      <ILO>53.00.51</ILO>
      <FPGA>2.00</FPGA>
      <MON>02.09</MON>
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      <Name>29.00</Name>
      <SFW>02.03</SFW>
      <ILO>53.00.51</ILO>
      <FPGA>2.00</FPGA>
      <MON>02.09</MON>
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      <Name>28.00</Name>
      <SFW>02.02</SFW>
      <ILO>53.00.42</ILO>
      <FPGA>2.00</FPGA>
      <MON>02.09</MON>
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      <Name>00.04</Name>
      <SFW>1.19</SFW>
      <ILO>88.24.96</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.9</MON>
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    <recipe>
      <Name>00.03</Name>
      <SFW>1.16</SFW>
      <ILO>53.00.10</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.9</MON>
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    <recipe>
      <Name>00.02</Name>
      <SFW>1.14</SFW>
      <ILO>53.00.10</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.9</MON>
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