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<recipe_info version="1.0.0">
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      <Name>26.36</Name>
      <SFW>1.95</SFW>
      <ILO>01.55.02</ILO>
      <FPGA>2.02</FPGA>
      <MON>2.09</MON>
    </recipe>
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      <Name>26.35</Name>
      <SFW>1.93</SFW>
      <ILO>01.54.03</ILO>
      <FPGA>2.02</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>26.34</Name>
      <SFW>1.92</SFW>
      <ILO>01.53.02</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>26.33</Name>
      <SFW>1.90</SFW>
      <ILO>01.53.02</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>26.32</Name>
      <SFW>1.90</SFW>
      <ILO>01.52.01</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>26.30</Name>
      <SFW>1.90</SFW>
      <ILO>01.51.02</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>26.22</Name>
      <SFW>1.80</SFW>
      <ILO>01.50.02</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>26.21</Name>
      <SFW>1.80</SFW>
      <ILO>01.50.02</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>26.20</Name>
      <SFW>1.80</SFW>
      <ILO>01.50.01</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>26.12</Name>
      <SFW>1.80</SFW>
      <ILO>01.41.01</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>26.06</Name>
      <SFW>1.20</SFW>
      <ILO>01.40.43</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>26.03</Name>
      <SFW>1.17</SFW>
      <ILO>01.40.43</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>26.00</Name>
      <SFW>1.17</SFW>
      <ILO>01.40.41</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
    </recipe>
    <recipe>
      <Name>25.00</Name>
      <SFW>1.15</SFW>
      <ILO>01.40.32</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>24.00</Name>
      <SFW>1.11</SFW>
      <ILO>01.40.23</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>23.00</Name>
      <SFW>1.1</SFW>
      <ILO>01.40.11</ILO>
      <FPGA>2.00</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>21.09</Name>
      <SFW>1.09</SFW>
      <ILO>01.30.30</ILO>
      <FPGA>1.14</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>21.08</Name>
      <SFW>1.09</SFW>
      <ILO>01.30.30</ILO>
      <FPGA>1.14</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>21.07</Name>
      <SFW>1.09</SFW>
      <ILO>01.30.30</ILO>
      <FPGA>1.14</FPGA>
      <MON>2.09</MON>
    </recipe>
    <recipe>
      <Name>21.05</Name>
      <SFW>1.09</SFW>
      <ILO>01.30.29</ILO>
      <FPGA>1.14</FPGA>
      <MON>2.09</MON>
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      <Name>20.00</Name>
      <SFW>1.08</SFW>
      <ILO>01.30.12</ILO>
      <FPGA>1.14</FPGA>
      <MON>2.09</MON>
    </recipe>
    <recipe>
      <Name>18.05</Name>
      <SFW>1.03</SFW>
      <ILO>01.20.17</ILO>
      <FPGA>1.13</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>18.04</Name>
      <SFW>1.03</SFW>
      <ILO>01.20.17</ILO>
      <FPGA>1.13</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>18.03</Name>
      <SFW>1.03</SFW>
      <ILO>01.20.17</ILO>
      <FPGA>1.13</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>18.02</Name>
      <SFW>1.03</SFW>
      <ILO>01.20.16</ILO>
      <FPGA>1.13</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>18.01</Name>
      <SFW>1.03</SFW>
      <ILO>01.20.14</ILO>
      <FPGA>1.13</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>18.00</Name>
      <SFW>1.01</SFW>
      <ILO>01.20.13</ILO>
      <FPGA>1.12</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>17.01</Name>
      <SFW>0.45</SFW>
      <ILO>01.20.09</ILO>
      <FPGA>1.12</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>17.00</Name>
      <SFW>0.45</SFW>
      <ILO>01.20.06</ILO>
      <FPGA>1.12</FPGA>
      <MON>2.09</MON>
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      <Name>16.00</Name>
      <SFW>0.44</SFW>
      <ILO>01.20.06</ILO>
      <FPGA>1.12</FPGA>
      <MON>2.09</MON>
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      <Name>15.01</Name>
      <SFW>0.43</SFW>
      <ILO>52.27.02</ILO>
      <FPGA>1.12</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>15.00</Name>
      <SFW>0.42</SFW>
      <ILO>52.27.02</ILO>
      <FPGA>1.12</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>14.0</Name>
      <SFW>0.41</SFW>
      <ILO>52.26.01</ILO>
      <FPGA>1.1</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>13.3</Name>
      <SFW>0.4</SFW>
      <ILO>52.24.06</ILO>
      <FPGA>1.1</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>13.2</Name>
      <SFW>0.39</SFW>
      <ILO>52.24.03</ILO>
      <FPGA>1.1</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>12.0</Name>
      <SFW>0.37</SFW>
      <ILO>52.22.06</ILO>
      <FPGA>1.07</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>11.2</Name>
      <SFW>0.36</SFW>
      <ILO>52.21.04</ILO>
      <FPGA>1.06</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>10.0</Name>
      <SFW>0.32</SFW>
      <ILO>52.20.02</ILO>
      <FPGA>1.03</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>9.0</Name>
      <SFW>0.31</SFW>
      <ILO>52.19.05</ILO>
      <FPGA>1.02</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>8.1</Name>
      <SFW>0.28</SFW>
      <ILO>52.18.05</ILO>
      <FPGA>1.01</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>8.0</Name>
      <SFW>0.26</SFW>
      <ILO>52.18.03</ILO>
      <FPGA>1</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>7.3</Name>
      <SFW>0.25</SFW>
      <ILO>52.17.09</ILO>
      <FPGA>0.14</FPGA>
      <MON>2.09</MON>
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    <recipe>
      <Name>7.1</Name>
      <SFW>0.22</SFW>
      <ILO>52.17.03</ILO>
      <FPGA>0.14</FPGA>
      <MON>2.09</MON>
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      <Name>6.0</Name>
      <SFW>0.2</SFW>
      <ILO>52.16.08</ILO>
      <FPGA>0.14</FPGA>
      <MON/>
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    <recipe>
      <Name>5.2</Name>
      <SFW>0.18</SFW>
      <ILO>52.15.03</ILO>
      <FPGA>0.13</FPGA>
      <MON/>
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    <recipe>
      <Name>4.2</Name>
      <SFW>0.11</SFW>
      <ILO>52.14.05</ILO>
      <FPGA>0.11</FPGA>
      <MON/>
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    <recipe>
      <Name>4.0</Name>
      <SFW>0.11</SFW>
      <ILO>52.14.04</ILO>
      <FPGA>0.11</FPGA>
      <MON/>
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    <recipe>
      <Name>3.2</Name>
      <SFW>0.1</SFW>
      <ILO>52.13</ILO>
      <FPGA>0.11</FPGA>
      <MON/>
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    <recipe>
      <Name>3.0</Name>
      <SFW>0.08</SFW>
      <ILO>53.12</ILO>
      <FPGA>0.11</FPGA>
      <MON/>
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    <recipe>
      <Name>2.0</Name>
      <SFW>0.07</SFW>
      <ILO>60.12</ILO>
      <FPGA>0.8</FPGA>
      <MON/>
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    <recipe>
      <Name>1.5</Name>
      <SFW>0.06</SFW>
      <ILO>60.11a</ILO>
      <FPGA>0.8</FPGA>
      <MON/>
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