/* Generated automatically by the program `genconstants'
   from the machine description file `md'.  */

#ifndef GCC_INSN_CONSTANTS_H
#define GCC_INSN_CONSTANTS_H

#define UNSPECV_RLC 302
#define UNSPEC_BITTEST_FOR_CARRY 6
#define UNSPEC_PSI_NYBBLE 100
#define UNSPEC_UNDEFINED 0
#define UNSPECV_NOP 200
#define REGNO_PC 0
#define UNSPECV_MPY_INHIBIT_INTR 100
#define UNSPECV_EINT 202
#define UNSPECV_READ_STATUS_REGISTER 203
#define UNSPECV_WRITE_STACK_POINTER 210
#define UNSPEC_POP_MULTI 21
#define UNSPECV_BIS_STATUS_REGISTER 206
#define UNSPECV_MWSHR8XOR 311
#define UNSPEC_LOAD_SP 105
#define UNSPEC_PUSH_MULTI 20
#define REGNO_FP 4
#define UNSPECV_BIC_STATUS_REGISTER 205
#define UNSPECV_BIC_SR_IRQ 207
#define UNSPECV_GET_WATCHDOG_CLEAR_VALUE 214
#define UNSPECV_GET_INTERRUPT_STATE 212
#define UNSPECV_DINT 201
#define UNSPECV_UNDEFINED 0
#define UNSPECV_SET_WATCHDOG_CLEAR_VALUE 215
#define UNSPECV_WRITE_STATUS_REGISTER 204
#define UNSPECV_RRC 303
#define UNSPECV_RRA 301
#define REGNO_SP 1
#define UNSPECV_MPY_RESTORE_INTR 101
#define UNSPECV_READ_STACK_POINTER 209
#define UNSPECV_BIS_SR_IRQ 208
#define REGNO_SR 2
#define UNSPECV_WATCHDOG_CLEAR 216
#define UNSPECV_CLRC 305
#define UNSPECV_SET_INTERRUPT_STATE 213
#define UNSPECV_MWSHL8XOR 310
#define UNSPECV_RRU 304
#define UNSPECV_DELAY_CYCLES 211
#define UNSPECV_RLA 300

#endif /* GCC_INSN_CONSTANTS_H */
