-- File: dff.vhd
-- Generated by MyHDL 0.7dev
-- Date: Thu Sep 30 16:28:38 2010


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_07dev.all;

entity dff is
    port (
        q: out std_logic;
        d: in std_logic;
        clk: in std_logic
    );
end entity dff;


architecture MyHDL of dff is


begin




DFF_LOGIC: process (clk) is
begin
    if rising_edge(clk) then
        q <= d;
    end if;
end process DFF_LOGIC;

end architecture MyHDL;
