-- File: latch.vhd
-- Generated by MyHDL 0.7dev
-- Date: Thu Sep 30 16:28:19 2010


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_07dev.all;

entity latch is
    port (
        q: out std_logic;
        d: in std_logic;
        g: in std_logic
    );
end entity latch;


architecture MyHDL of latch is


begin




LATCH_LOGIC: process (d, g) is
begin
    if (g = '1') then
        q <= d;
    end if;
end process LATCH_LOGIC;

end architecture MyHDL;
