// File: latch.v
// Generated by MyHDL 0.7dev
// Date: Thu Sep 30 16:28:19 2010


`timescale 1ns/10ps

module latch (
    q,
    d,
    g
);


output q;
reg q;
input d;
input g;






always @(d, g) begin: LATCH_LOGIC
    if ((g == 1)) begin
        q <= d;
    end
end

endmodule
