JITCORE_PPC_REG_EXPAND(R0, 32)
JITCORE_PPC_REG_EXPAND(R1, 32)
JITCORE_PPC_REG_EXPAND(R2, 32)
JITCORE_PPC_REG_EXPAND(R3, 32)
JITCORE_PPC_REG_EXPAND(R4, 32)
JITCORE_PPC_REG_EXPAND(R5, 32)
JITCORE_PPC_REG_EXPAND(R6, 32)
JITCORE_PPC_REG_EXPAND(R7, 32)
JITCORE_PPC_REG_EXPAND(R8, 32)
JITCORE_PPC_REG_EXPAND(R9, 32)
JITCORE_PPC_REG_EXPAND(R10, 32)
JITCORE_PPC_REG_EXPAND(R11, 32)
JITCORE_PPC_REG_EXPAND(R12, 32)
JITCORE_PPC_REG_EXPAND(R13, 32)
JITCORE_PPC_REG_EXPAND(R14, 32)
JITCORE_PPC_REG_EXPAND(R15, 32)
JITCORE_PPC_REG_EXPAND(R16, 32)
JITCORE_PPC_REG_EXPAND(R17, 32)
JITCORE_PPC_REG_EXPAND(R18, 32)
JITCORE_PPC_REG_EXPAND(R19, 32)
JITCORE_PPC_REG_EXPAND(R20, 32)
JITCORE_PPC_REG_EXPAND(R21, 32)
JITCORE_PPC_REG_EXPAND(R22, 32)
JITCORE_PPC_REG_EXPAND(R23, 32)
JITCORE_PPC_REG_EXPAND(R24, 32)
JITCORE_PPC_REG_EXPAND(R25, 32)
JITCORE_PPC_REG_EXPAND(R26, 32)
JITCORE_PPC_REG_EXPAND(R27, 32)
JITCORE_PPC_REG_EXPAND(R28, 32)
JITCORE_PPC_REG_EXPAND(R29, 32)
JITCORE_PPC_REG_EXPAND(R30, 32)
JITCORE_PPC_REG_EXPAND(R31, 32)

JITCORE_PPC_REG_EXPAND(PC, 32)
JITCORE_PPC_REG_EXPAND(LR, 32)
JITCORE_PPC_REG_EXPAND(CTR, 32)
JITCORE_PPC_REG_EXPAND(MSR, 32)

JITCORE_PPC_REG_EXPAND(XER_SO, 32)
JITCORE_PPC_REG_EXPAND(XER_OV, 32)
JITCORE_PPC_REG_EXPAND(XER_CA, 32)
JITCORE_PPC_REG_EXPAND(XER_BC, 32)

JITCORE_PPC_REG_EXPAND(CR0_LT, 8)
JITCORE_PPC_REG_EXPAND(CR0_GT, 8)
JITCORE_PPC_REG_EXPAND(CR0_EQ, 8)
JITCORE_PPC_REG_EXPAND(CR0_SO, 8)
JITCORE_PPC_REG_EXPAND(CR1_LT, 8)
JITCORE_PPC_REG_EXPAND(CR1_GT, 8)
JITCORE_PPC_REG_EXPAND(CR1_EQ, 8)
JITCORE_PPC_REG_EXPAND(CR1_SO, 8)
JITCORE_PPC_REG_EXPAND(CR2_LT, 8)
JITCORE_PPC_REG_EXPAND(CR2_GT, 8)
JITCORE_PPC_REG_EXPAND(CR2_EQ, 8)
JITCORE_PPC_REG_EXPAND(CR2_SO, 8)
JITCORE_PPC_REG_EXPAND(CR3_LT, 8)
JITCORE_PPC_REG_EXPAND(CR3_GT, 8)
JITCORE_PPC_REG_EXPAND(CR3_EQ, 8)
JITCORE_PPC_REG_EXPAND(CR3_SO, 8)
JITCORE_PPC_REG_EXPAND(CR4_LT, 8)
JITCORE_PPC_REG_EXPAND(CR4_GT, 8)
JITCORE_PPC_REG_EXPAND(CR4_EQ, 8)
JITCORE_PPC_REG_EXPAND(CR4_SO, 8)
JITCORE_PPC_REG_EXPAND(CR5_LT, 8)
JITCORE_PPC_REG_EXPAND(CR5_GT, 8)
JITCORE_PPC_REG_EXPAND(CR5_EQ, 8)
JITCORE_PPC_REG_EXPAND(CR5_SO, 8)
JITCORE_PPC_REG_EXPAND(CR6_LT, 8)
JITCORE_PPC_REG_EXPAND(CR6_GT, 8)
JITCORE_PPC_REG_EXPAND(CR6_EQ, 8)
JITCORE_PPC_REG_EXPAND(CR6_SO, 8)
JITCORE_PPC_REG_EXPAND(CR7_LT, 8)
JITCORE_PPC_REG_EXPAND(CR7_GT, 8)
JITCORE_PPC_REG_EXPAND(CR7_EQ, 8)
JITCORE_PPC_REG_EXPAND(CR7_SO, 8)

JITCORE_PPC_REG_EXPAND(SPRG0, 32)
JITCORE_PPC_REG_EXPAND(SPRG1, 32)
JITCORE_PPC_REG_EXPAND(SPRG2, 32)
JITCORE_PPC_REG_EXPAND(SPRG3, 32)
JITCORE_PPC_REG_EXPAND(SRR0, 32)
JITCORE_PPC_REG_EXPAND(SRR1, 32)
JITCORE_PPC_REG_EXPAND(DAR, 32)
JITCORE_PPC_REG_EXPAND(DSISR, 32)
JITCORE_PPC_REG_EXPAND(PIR, 32)
JITCORE_PPC_REG_EXPAND(PVR, 32)
JITCORE_PPC_REG_EXPAND(DEC, 32)
JITCORE_PPC_REG_EXPAND(TBL, 32)
JITCORE_PPC_REG_EXPAND(TBU, 32)
